cv
Table of contents
- General Information
- Education
- Research Interests
- Publications
- Awards and Honors
- Experience
- Research Experience
- Teaching Experience
- Skills
- Training
- Chip Designs
- Professional Services
General Information
| Full Name | Hyunwoo Oh |
| Date of Birth | 16th January 1995 |
| Languages | Korean, English |
Education
-
2021 Seoul
B.S. in Electronic Engineering
Seoul National University of Science and Technology, Korea
Research Interests
-
Computer Architecture
- Exploring novel HW architecture and methodologies to meet the growing computing performance and efficiency demands.
- Heterogeneous Computing: Designing the optimized processor architectures that integrate both emerging parallel machines (PIM, NPU, etc.) and conventional general-purpose processors.
- Compilers: Developing SW compilers optimized for targeted HW designs.
-
HW/SW Co-design
- Developing techniques for co-optimization to improve energy efficiency and performance.
- Parameterized HW Design Framework: Designing configurable, scalable architectures with RTL generators, compilers, and SW stacks to tailor the HW to system constraints such as power, energy, and area.
- Partitioning Methodology: Investigating a method to derive the parameters to mitigate the impact of Amdahl’s law and maximize system performance.
Publications
Awards and Honors
Experience
-
2023.01 - present Pangyo, Gyeonggi
Junior Engineer
Infra Technology R&D Center, Hanwha Systems, Korea - Designed SoC FPGA-based integrated thermal image processor for infrared focal plane arrays. [DSD 2023 (C8)]
- Developed of the RTOS for Heterogeneous MPSoC using the TI Vision SDK platform.
-
2019.03 - 2023.02 Seoul
Research Assistant
SoC Platform Lab., Seoul National University of Science and Technology, Korea - Worked on several research projects funded by the various national institutes (See Research Experience section).
Research Experience
-
2022.07-2022.12 Seoul
Development for Processing Software on AI Semiconductor Devices
Seoul National University of Science and Technology, Korea - Funder: Ministry of Science and ICT, Korea
- My contributions
- Designed the RISC processor with a custom instruction set extension for flexible AI acceleration for edge devices. [IEEE Access 2023 (J6)]
- Researched optimized hardware and software architecture for applying posit number format to previous applications based on IEEE-754. [ISLPED 2023 (C6)] [ISOCC 2022 (C5)]
-
2022.04-2022.12 Seoul
Development of DRAM PIM Semiconductor Technology For Enhanced Computing Function for Edge
Seoul National University of Science and Technology, Korea - Funder: Ministry of Science and ICT, Korea
- My contributions
- Designed a top-level hierarchical hardware architecture for PIM based on DRAM, and a software simulator architecture.
-
2022.03-2022.12 Seoul
Next-Generation System Semiconductor Design Engineer Development Program
Seoul National University of Science and Technology, Korea - Funder: Ministry of Trade, Industry and Energy, Korea
- My contributions
- Building a verification environment for LIN peripheral IP, including scripts for Synopsys EDA tools, a randomized testbench generator, and the software driver. [ICCE 2022 (C4)]
-
2020.03-2022.03 Seoul
Multi-core Hardware Accelerator for High-Performance Computing (HPC)
Seoul National University of Science and Technology, Korea - Funder: Ministry of Science and ICT, Korea
- My contributions
- Researched processor architecture to provide a platform for building an accelerator-rich environment. [ISOCC 2020 (C1)]
-
2020.03-2021.12 Seoul
Development of Embedded Artificial Intelligence Module and System Based on Neuromorphic
Seoul National University of Science and Technology, Korea - Funder: Ministry of Trade, Industry and Energy, Korea
- My contributions
- Developed the parameterized HDL generator software for an embedded AI module. [Micromachines 2021 (J3)]
- Researched applications of the AI module. [JICCE 2022 (J5)] [Micromachines 2021 (J4)] [ICFICE 2022 (C3)] [ICCE 2021 (C2)]
-
2020.03-2021.12 Seoul
Development of Light-weight SW-SoC Solution for Respiratory Medical Device
Seoul National University of Science and Technology, Korea - Funder: Ministry of Trade, Industry and Energy, Korea
- My contributions
- Designed a 2D graphics accelerator architecture optimized for graph visualization tasks in medical devices. [Electronics 2021 (J2)]
- Developed a software stack for hardware implementation of Lempel-Ziv 77 lossless decompression accelerator. [Micromachines 2021 (J1)]
Teaching Experience
-
Fall, 2021 Seoul
Teaching Assisant for "Computer Architecture"
Seoul National University of Science and Technology, Korea BSc Electronic Engineering, Year 3 -
Spring, 2021 Seoul
Teaching Assisant for "Digital System Design"
Seoul National University of Science and Technology, Korea BSc Electronic Engineering, Year 3
Skills
| Computer Languages | C, C++, Python, MATLAB, R |
| Hardware Description | Verilog, SystemVerilog, Chisel |
| HDL Simulation Tools | VCS, ModelSim, Verilator |
| FPGA Tools | Vivado, Vitis, Quartus II/Prime, Nios II EDS |
| Synopsys EDA Tools | Design Compiler, Memory Compiler, IC Compiler I/II, PrimeTime, Formality, StarRCXT, VCS, Verdi |
| Cadence EDA Tools | Virtuoso Layout Suite, Calibre DRC/LVS |
| Cadence CAD Tools | OrCAD Capture, Allegro PCB Designer |
| Operating Systems | FreeRTOS, TI Vision SDK, PetaLinux |
Training
-
2023.01 ISO 26262:2018 Functional Safety Engineering Course: Automotive Foundation Level (FSE-AFL)
Det Norske Veritas
Chip Designs
-
2021.07 
32-bit Processor with Posit Arithmetic Coprocessor for Embedded Systems
Professional Services
-
Reviwer Activities
- IEEE Access, 2 times since 2023