ALGORITHM · ARCHITECTURE · SYSTEMS

Efficient AI, from models to machines.

I design efficient systems for emerging AI through algorithm, software, and hardware co-design—from low-bit inference to accelerators for emerging ML workloads and brain-inspired computing.

01 / EFFICIENT LLM INFERENCE

Scalable low-bit ML on everyday processors

Large models quickly become memory- and compute-bound at the edge. I develop end-to-end quantization frameworks, CUDA/CPU kernels, and small architectural extensions that make fine-grained low-bit execution practical on general-purpose CPUs.

T-SAR ISA extension mapped onto x86 AVX2 SIMD with ternary LUT and GEMV instructions — **T-SAR** · ISA and microarchitecture realization on x86 AVX2 SIMDPaper ↗

T-SAR comparison of memory-based LUT execution and in-register LUT generation — **T-SAR** · Memory LUTs versus on-the-fly generation in SIMD registersPaper ↗

PolyQ motivation comparing uniform and fine-grained channel-wise quantization — **PolyQ** · Fine-grained precision fits fractional edge-memory budgets

Methods & keywords

Mixed-precision
Low-bit quantization
CPU SIMD
In-register computing
Compiler co-design
Edge LLMs

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2026

ICCAD

PolyQ comparison of uniform and fine-grained mixed-precision quantization

PolyQ: Codesigning End-to-End Quantization Framework for Scalable Edge CPU LLM Inference

Hyunwoo Oh, Suyeon Jang, Hanning Chen, KyungIn Nam, Sanggeon Yun, Ryozo Masukawa, and Mohsen Imani

ICCAD 2026 PolyQ: Codesigning End-to-End Quantization Framework for Scalable Edge CPU LLM Inference, Hyunwoo Oh et al.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov 2026, pp. 1–9

Accepted

BibTeX

@inproceedings{oh_polyq_2026,
  address = {San Jose, CA, USA},
  title = {{PolyQ: Codesigning End-to-End Quantization Framework for Scalable Edge CPU LLM Inference}},
  booktitle = {{IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
  author = {Oh, Hyunwoo and Jang, Suyeon and Chen, Hanning and Nam, KyungIn and Yun, Sanggeon and Masukawa, Ryozo and Imani, Mohsen},
  month = nov,
  year = {2026},
  pages = {1--9},
}

ICCAD

ExaGEMM associative in-register low-bit matrix multiplication framework

ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM

Hyunwoo Oh, Suyeon Jang, Hanning Chen, Sanggeon Yun, Ryozo Masukawa, and Mohsen Imani

ICCAD 2026 ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM, Hyunwoo Oh et al.

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov 2026, pp. 1–9

Accepted

BibTeX

@inproceedings{oh_exagemm_2026,
  address = {San Jose, CA, USA},
  title = {{ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM}},
  booktitle = {{IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
  author = {Oh, Hyunwoo and Jang, Suyeon and Chen, Hanning and Yun, Sanggeon and Masukawa, Ryozo and Imani, Mohsen},
  month = nov,
  year = {2026},
  pages = {1--9},
}

DATE
T-SAR: A Full-Stack Co-design for CPU-Only Ternary LLM Inference via In-Place SIMD ALU Reorganization

Hyunwoo Oh, KyungIn Nam, Rajat Bhattacharjya, Hanning Chen, Tamoghno Das, Sanggeon Yun, Suyeon Jang, Andrew Ding, Nikil Dutt, and Mohsen Imani

DATE 2026 T-SAR: A Full-Stack Co-design for CPU-Only Ternary LLM Inference via In-Place SIMD ALU Reorganization, Hyunwoo Oh et al.

Design, Automation and Test in Europe Conference (DATE), Verona, Italy, Apr 2026, pp. 1–7

Abstract BibTeX HTML

Recent advances in LLMs have outpaced the computational and memory capacities of edge platforms that primarily employ CPUs, thereby challenging efficient and scalable deployment. While ternary quantization enables significant resource savings, existing CPU solutions rely heavily on memory-based lookup tables (LUTs) which limit scalability, and FPGA or GPU accelerators remain impractical for edge use. This paper presents T-SAR, the first framework to achieve scalable ternary LLM inference on CPUs by repurposing the SIMD register file for dynamic, in-register LUT generation with minimal hardware modifications. T-SAR eliminates memory bottlenecks and maximizes data-level parallelism, delivering 5.6-24.5x and 1.1-86.2x improvements in GEMM latency and GEMV throughput, respectively, with only 3.2% power and 1.4% area overheads in SIMD units. T-SAR achieves up to 2.5-4.9x the energy efficiency of an NVIDIA Jetson AGX Orin, establishing a practical approach for efficient LLM inference on edge platforms.
@inproceedings{oh_tsar_2026, address = {Verona, Italy}, title = {{T-SAR: A Full-Stack Co-design for CPU-Only Ternary LLM Inference via In-Place SIMD ALU Reorganization}}, isbn = {}, doi = {10.23919/DATE69613.2026.11539096}, booktitle = {{Design, Automation and Test in Europe Conference (DATE)}}, author = {Oh, Hyunwoo and Nam, KyungIn and Bhattacharjya, Rajat and Chen, Hanning and Das, Tamoghno and Yun, Sanggeon and Jang, Suyeon and Ding, Andrew and Dutt, Nikil and Imani, Mohsen}, month = apr, year = {2026}, pages = {1--7}, }

02 / EMERGING ML ACCELERATORS

Accelerators for emerging ML workloads

Emerging ML workloads expose bottlenecks that conventional hardware handles poorly. I turn their compute, memory, and dataflow characteristics into specialized accelerators, carrying each design from algorithm and architecture co-design through implementation and end-to-end evaluation across vision, language, graph, and multimodal AI.

TRINE accelerator architecture, reconfigurable processing unit, and mode-switchable engine — **TRINE** · Runtime-adaptive multimodal FPGA acceleratorPaper ↗

QUILL analysis of cache-locality, arithmetic-intensity, and bank-conflict bottlenecks in deformable attention — **QUILL** · The three bottlenecks: scattered access, low arithmetic intensity, and bank conflictsPaper ↗

QUILL cache-local deformable attention accelerator overview — **QUILL** · Mitigation through query reordering, caching, and fused executionPaper ↗

Methods & keywords

ML acceleration
Domain-specific architectures
Reconfigurable computing
Memory systems
Hardware–software co-design
Edge AI

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2026

DAC
TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI

Hyunwoo Oh, Hanning Chen, Sanggeon Yun, Yang Ni, Suyeon Jang, Behnam Khaleghi, Fei Wen, and Mohsen Imani

DAC 2026 TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI, Hyunwoo Oh et al.

ACM/IEEE Design Automation Conference (DAC), Long Beach, CA, USA, Jul 2026, pp. 1–7

Accepted

Abstract BibTeX HTML

Multimodal stacks that mix ViTs, CNNs, GNNs, and transformer NLP strain embedded platforms because their compute/memory patterns diverge and hard real-time targets leave little slack. TRINE is a single-bitstream FPGA accelerator and compiler that executes end-to-end multimodal inference without reconfiguration. Layers are unified as DDMM/SDDMM/SpMM and mapped to a mode0switchable engine that toggles at runtime among weight/output stationary systolic, 1×CS SIMD, and a routable adder tree (RADT) on a shared PE array. A width-matched, two-stage top-k unit enables in-stream token pruning, while dependency-aware layer offloading (DALO) overlaps independent kernels across reconfigurable processing units to sustain utilization. Evaluated on Alveo U50 and ZCU104, TRINE reduces latency by up to 22.57× vs. RTX 4090 and 6.86× vs. Jetson Orin Nano at 20–21 W; token pruning alone yields up to 7.8× on ViT-heavy pipelines, and DALO contributes up to 79% throughput improvement. With int8 quantization, accuracy drops remain <2.5% across representative tasks, delivering state-of-theart latency and energy efficiency for unified vision, language, and graph workloads—in one bitstream.
@inproceedings{oh_trine_2026, address = {Long Beach, CA, USA}, title = {{TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI}}, isbn = {}, url = {}, doi = {}, booktitle = {{ACM/IEEE Design Automation Conference (DAC)}}, author = {Oh, Hyunwoo and Chen, Hanning and Yun, Sanggeon and Ni, Yang and Jang, Suyeon and Khaleghi, Behnam and Wen, Fei and Imani, Mohsen}, month = jul, year = {2026}, pages = {1--7}, }
DATE
QUILL: An Algorithm-Architecture Co-Design for Cache-Local Deformable Attention

Hyunwoo Oh, Hanning Chen, Sanggeon Yun, Yang Ni, Wenjun Huang, Tamoghno Das, Suyeon Jang, and Mohsen Imani

DATE 2026 QUILL: An Algorithm-Architecture Co-Design for Cache-Local Deformable Attention, Hyunwoo Oh et al.

Design, Automation and Test in Europe Conference (DATE), Verona, Italy, Apr 2026, pp. 1–7

Abstract BibTeX HTML

Deformable transformers deliver state-of-the-art detection but map poorly to hardware due to irregular memory access and low arithmetic intensity. We introduce QUILL, a schedule-aware accelerator that turns deformable attention into cache-friendly, single-pass work. At its core, Distance-based Out-of-Order Querying (DOOQ) orders queries by spatial proximity; the look-ahead drives a region prefetch into an alternate buffer–forming a schedule-aware prefetch loop that overlaps memory and compute. A fused MSDeformAttn engine executes interpolation, Softmax, aggregation, and the final projection (W”m) in one pass without spilling intermediates, while small tensors are kept on-chip and surrounding dense layers run on integrated GEMMs. Implemented as RTL and evaluated end-to-end, QUILL achieves up to 7.29x higher throughput and 47.3x better energy efficiency than an RTX 4090, and exceeds prior accelerators by 3.26-9.82x in throughput and 2.01-6.07x in energy efficiency. With mixed-precision quantization, accuracy tracks FP32 within <=0.9 AP across Deformable and Sparse DETR variants. By converting sparsity into locality–and locality into utilization–QUILL delivers consistent, end-to-end speedups.
@inproceedings{oh_quill_2026, address = {Verona, Italy}, title = {{QUILL: An Algorithm-Architecture Co-Design for Cache-Local Deformable Attention}}, isbn = {}, doi = {10.23919/DATE69613.2026.11539507}, booktitle = {{Design, Automation and Test in Europe Conference (DATE)}}, author = {Oh, Hyunwoo and Chen, Hanning and Yun, Sanggeon and Ni, Yang and Huang, Wenjun and Das, Tamoghno and Jang, Suyeon and Imani, Mohsen}, month = apr, year = {2026}, pages = {1--7}, }
DATE
RIFT: A Single-Bitstream, Runtime-Adaptive FPGA-Based Accelerator for Multimodal AI

Hyunwoo Oh, KyungIn Nam, Rajat Bhattacharjya, Hanning Chen, Tamoghno Das, Sanggeon Yun, Suyeon Jang, Andrew Ding, Nikil Dutt, and Mohsen Imani

DATE 2026 RIFT: A Single-Bitstream, Runtime-Adaptive FPGA-Based Accelerator for Multimodal AI, Hyunwoo Oh et al.

Design, Automation and Test in Europe Conference (DATE), Verona, Italy, Apr 2026, pp. 1–3

Abstract BibTeX HTML

Multimodal models spanning ViTs, CNNs, GNNs, and transformer NLP stress embedded systems because their heterogeneous compute and memory behaviors complicate resource allocation, load balancing, and real-time inference. We present RIFT, a single-bitstream FPGA accelerator and compiler for end-to-end multimodal inference. RIFT unifies layers as DDMM/SDDMM/SpMM kernels executed on a runtime mode-switchable engine that morphs among weight-/output-stationary systolic, 1×CS SIMD, and a routable adder tree (RADT) on a shared datapath. A two-stage hardware top-k unit, width-matched to the array, performs in-stream token pruning with minimal buffering, and dependency-aware layer offloading (DALO) overlaps independent kernels across multiple RPUs—achieving adaptation without bitstream reconfiguration. On Alveo U50 and ZCU104, RIFT reduces latency by up to 22.57× versus an RTX 4090 and 6.86× versus a Jetson Orin Nano at ∼20–21 W; pruning alone yields up to 7.8× on ViT-heavy workloads. Ablations isolate contributions, with DALO improving throughput by up to 79%. Compared to prior FPGA designs, RIFT delivers state-of-the-art latency and energy efficiency across vision, language, and graph workloads in a single bitstream.
@inproceedings{oh_rift_2026, address = {Verona, Italy}, title = {{RIFT: A Single-Bitstream, Runtime-Adaptive FPGA-Based Accelerator for Multimodal AI}}, isbn = {}, doi = {10.23919/DATE69613.2026.11539726}, booktitle = {{Design, Automation and Test in Europe Conference (DATE)}}, author = {Oh, Hyunwoo and Nam, KyungIn and Bhattacharjya, Rajat and Chen, Hanning and Das, Tamoghno and Yun, Sanggeon and Jang, Suyeon and Ding, Andrew and Dutt, Nikil and Imani, Mohsen}, month = apr, year = {2026}, pages = {1--3}, }

2025

FCCM
A Multimodal AI Acceleration with Dynamic Pruning and Run-time Configuration

Hyun Woo Oh, Hanning Chen, Sanggeon Yun, Yang Ni, Behnam Khaleghi, Fei Wen, and Mohsen Imani

FCCM 2025 A Multimodal AI Acceleration with Dynamic Pruning and Run-time Configuration, Hyun Woo Oh et al.

IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Fayetteville, AR, USA, May 2025

Abstract BibTeX HTML PDF Poster

The computational diversity of multimodal AI workloads—spanning vision transformers (ViTs), graph neural networks (GNNs), CNNs, and transformer-based NLP—poses a fundamental challenge to embedded acceleration platforms. We propose a fully integrated FPGA-based acceleration framework that addresses this heterogeneity via compile-time and runtime configurability. Our system introduces a reconfigurable processing unit (RPU) capable of executing dense and sparse matrix operations (DDMM, SpMM, SDDMM), a scalable top-k pruning engine for ViTs, and a domain-specific compiler for hardware-software co-design. The architecture supports real-time configuration without reloading bitstreams, enabling unified deployment across tasks. Implementations on Xilinx U50 and ZCU104 demonstrate up to 22.57× and 6.86× latency reductions versus RTX 4090 and Jetson Orin Nano, respectively, validating the design’s efficiency for real-time, resource-limited environments.
@inproceedings{oh_multimodal_2025, address = {Fayetteville, AR, USA}, title = {{A Multimodal AI Acceleration with Dynamic Pruning and Run-time Configuration}}, isbn = {}, doi = {10.1109/FCCM62733.2025.00072}, booktitle = {{IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)}}, author = {Oh, Hyun Woo and Chen, Hanning and Yun, Sanggeon and Ni, Yang and Khaleghi, Behnam and Wen, Fei and Imani, Mohsen}, month = may, year = {2025}, }

03 / BRAIN-INSPIRED COMPUTING

Brain-inspired learning and reasoning

Hyperdimensional computing represents information with distributed high-dimensional vectors, enabling noise-tolerant learning and reasoning. I codesign these representations with cache-oriented and memory-aware architectures for efficient perception and decisions.

TorR end-to-end brain-inspired object detection training and inference framework — **TorR** · End-to-end training and inference frameworkPaper ↗

TorR cache-gated associative aligner and HDC graph reasoner — **TorR** · Cache-gated HDC aligner and graph reasonerPaper ↗

Methods & keywords

Hyperdimensional computing
Associative memory
Partial-similarity reuse
Robust learning
Reasoning

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2026

DAC
TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design

Hyunwoo Oh, SungHeon Jeong, Suyeon Jang, Hanning Chen, Sanggeon Yun, Tamoghno Das, and Mohsen Imani

DAC 2026 TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design, Hyunwoo Oh et al.

ACM/IEEE Design Automation Conference (DAC), Long Beach, CA, USA, Jul 2026, pp. 1–7

Accepted

Abstract BibTeX HTML

Task-oriented object detection (TOOD) atop CLIP offers open-vocabulary, prompt-driven semantics, yet dense per-window computation and heavy memory traffic hinder real-time, power-limited edge deployment. We present TorR, a brain-inspired algorithm–architecture co-design that replaces CLIP-style dense alignment with a hyperdimensional (HDC) associative reasoner and turns temporal coherence into reuse. On the algorithm side, TorR reformulates alignment as HDC similarity and graph composition, introducing partial-similarity reuse via (i) query caching with per-class score accumulation, (ii) exact 𝛿-updates when only a small set of hypervector bits change, and (iii) similarity/load-gated bypass under high system load. On the architecture side, TorR instantiates a lane-scalable, bit-sliced item memory with bank/precision gating and a lightweight controller that schedules bypass/𝛿/full paths to meet RT-30/RT-60 targets as object counts vary. Synthesized in a TSMC 28 nm process and exercised with a cycle-accurate simulator, TorR sustains real-time throughput with millijoule-scale energy per window (≈50 mJ at 60 FPS; ≈113 mJ at 30 FPS) and low latency jitter, while delivering competitive AP@0.5 across five task prompts (mean 44.27%) within a bounded margin to strong VLM baselines, but at orders-of-magnitude lower energy. The design exposes deployment-time configurability (effective dimension 𝐷′, thresholds, precision) to trade accuracy, latency, and energy for edge budgets.
@inproceedings{oh_torr_2026, address = {Long Beach, CA, USA}, title = {{TorR: Towards Brain-Inspired Task-Oriented Reasoning via Cache-Oriented Algorithm-Architecture Co-design}}, isbn = {}, url = {}, doi = {}, booktitle = {{ACM/IEEE Design Automation Conference (DAC)}}, author = {Oh, Hyunwoo and Jeong, SungHeon and Jang, Suyeon and Chen, Hanning and Yun, Sanggeon and Das, Tamoghno and Imani, Mohsen}, month = jul, year = {2026}, pages = {1--7}, }

ICASSP

HYPERDOA: Robust and Efficient DoA Estimation Using Hyperdimensional Computing

Rajat Bhattacharjya, Woohyeok Park, Arnab Sarkar, Hyunwoo Oh, Mohsen Imani, and Nikil Dutt

ICASSP 2026 HYPERDOA: Robust and Efficient DoA Estimation Using Hyperdimensional Computing, Rajat Bhattacharjya, Woohyeok Park, Arnab Sarkar, Hyunwoo Oh et al.

IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Barcelona, Spain, May 2026, pp. 20841-20845

BibTeX HTML

@inproceedings{bhattacharjya_hyperdoa_2026,
  address = {Barcelona, Spain},
  title = {{HYPERDOA: Robust and Efficient DoA Estimation Using Hyperdimensional Computing}},
  author = {Bhattacharjya, Rajat and Park, Woohyeok and Sarkar, Arnab and Oh, Hyunwoo and Imani, Mohsen and Dutt, Nikil},
  booktitle = {IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)},
  year = {2026},
  month = may,
  pages = {20841-20845},
  doi = {10.1109/ICASSP55912.2026.11464439},
}

DATE
DecoHD: Decomposed Hyperdimensional Classification under Extreme Memory Budgets

Sanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, and Mohsen Imani

DATE 2026 DecoHD: Decomposed Hyperdimensional Classification under Extreme Memory Budgets, Sanggeon Yun, Hyunwoo Oh et al.

Design, Automation and Test in Europe Conference (DATE), Verona, Italy, Apr 2026, pp. 1–7

Abstract BibTeX HTML

Decomposition is a proven way to shrink deep networks without changing I/O. We bring this idea to hyperdimensional computing (HDC), where footprint cuts usually shrink the feature axis and erode concentration and robustness. Prior HDC decompositions decode via fixed atomic hypervectors, which are ill-suited for compressing learned class prototypes. We introduce DecoHD, which learns directly in a decomposed HDC parameterization: a small, shared set of per-layer channels with multiplicative binding across layers and bundling at the end, yielding a large representational space from compact factors. DecoHD compresses along the class axis via a lightweight bundling head while preserving native bind-bundle-score; training is end-to-end, and inference remains pure HDC, aligning with in/near-memory accelerators. In evaluation, DecoHD attains extreme memory savings with only minor accuracy degradation under tight deployment budgets. On average it stays within about 0.1-0.15% of a strong non-reduced HDC baseline (worst case 5.7%), is more robust to random bit-flip noise, reaches its accuracy plateau with up to 97% fewer trainable parameters, and – in hardware – delivers roughly 277x/35x energy/speed gains over a CPU (AMD Ryzen 9 9950X), 13.5x/3.7x over a GPU (NVIDIA RTX 4090), and 2.0x/2.4x over a baseline HDC ASIC.
@inproceedings{yun_decohd_2026, address = {Verona, Italy}, title = {{DecoHD: Decomposed Hyperdimensional Classification under Extreme Memory Budgets}}, isbn = {}, url = {}, doi = {}, booktitle = {{Design, Automation and Test in Europe Conference (DATE)}}, author = {Yun, Sanggeon and Oh, Hyunwoo and Masukawa, Ryozo and Imani, Mohsen}, month = apr, year = {2026}, pages = {1--7}, }
DATE
LogHD: Robust Compression of Hyperdimensional Classifiers via Logarithmic Class-Axis Reduction

Sanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, Pietro Mercati, Nathaniel D Bastian, and Mohsen Imani

DATE 2026 LogHD: Robust Compression of Hyperdimensional Classifiers via Logarithmic Class-Axis Reduction, Sanggeon Yun, Hyunwoo Oh et al.

Design, Automation and Test in Europe Conference (DATE), Verona, Italy, Apr 2026, pp. 1–7

Abstract BibTeX HTML

Hyperdimensional computing (HDC) suits memory, energy, and reliability-constrained systems, yet the standard "one prototype per class" design requires O(CD) memory (with C classes and dimensionality D). Prior compaction reduces D (feature axis), improving storage/compute but weakening robustness. We introduce LogHD, a logarithmic class-axis reduction that replaces the C per-class prototypes with n≈⌈logkC⌉ bundle hypervectors (alphabet size k) and decodes in an n-dimensional activation space, cutting memory to O(DlogkC) while preserving D. LogHD uses a capacity-aware codebook and profile-based decoding, and composes with feature-axis sparsification. Across datasets and injected bit flips, LogHD attains competitive accuracy with smaller models and higher resilience at matched memory. Under equal memory, it sustains target accuracy at roughly 2.5-3.0× higher bit-flip rates than feature-axis compression; an ASIC instantiation delivers 498× energy efficiency and 62.6× speedup over an AMD Ryzen 9 9950X and 24.3×/6.58× over an NVIDIA RTX 4090, and is 4.06× more energy-efficient and 2.19× faster than a feature-axis HDC ASIC baseline.
@inproceedings{yun_loghd_2026, address = {Verona, Italy}, title = {{LogHD: Robust Compression of Hyperdimensional Classifiers via Logarithmic Class-Axis Reduction}}, isbn = {}, url = {}, doi = {}, booktitle = {{Design, Automation and Test in Europe Conference (DATE)}}, author = {Yun, Sanggeon and Oh, Hyunwoo and Masukawa, Ryozo and Mercati, Pietro and Bastian, Nathaniel D and Imani, Mohsen}, month = apr, year = {2026}, pages = {1--7}, }

ACROSS THE STACK

From model transformations to RTL and real systems.

My goal is to make ambitious AI workloads deployable under real constraints—not only faster in isolation, but efficient end to end.

Browse all publications